Because low temperature poly-silicon (LIPS) has a high electron mobility, the area of devices of a thin film transistor (TFT) can be reduced effectively, thereby improving an opening rate of a pixel. Not only can the brightness of a display panel be raised, but also the entire energy consumption is reduced at the same time, so as to decrease the fabricating cost of the display panel significantly.
Please refer to FIG. 1, which is a cross-sectional schematic diagram of a conventional array substrate 10. The array substrate 10 comprises a substrate 101, a buffer layer 102, a light shielding layer 103, a polysilicon layer 104, an insulating layer 105, a gate 106, two interlayer connecting layers 107A and 108B, a source 108A, a drain 108B, an insulating layer 109, a conductive layer 110, an insulating layer 111, and a conductive layer 112. Top gate structures are all used in the conventional array substrate. The purpose of fabricating a self-aligned light doped drain (LDD) is achieved by the top gate shielding a channel, for reducing the overlapping of the drain and the LDD. However, the conventional method of fabricating a complementary metal oxide semiconductor (CMOS) needs 11 masks, therefore the process is complex, the fabricating cost is relatively high, and the product yield is difficult to improve.
As a result, it is necessary to provide an array substrate and a method of fabricating the same to solve the problems existing in the conventional technologies.